Some papers, presentations, and tutorials I've written:

Open Digital HDL to Synthesized Layout Flow for Mixed-Signal IC's. Final draft of my master's thesis.

Thesis Defense Presentation.

Fault Testable Design of Asynchronous Sequential Circuits. An overview of some asynchronous testability principals for EE 861.

Arbiter for an Asynchronous Counterflow Pipeline. A proposal and design for a simple arbiter to handle instruction flows in a special type of asynchronous processor. It was meant as a design project for a VLSI class, but the group decided not to implement it.

An Introduction to Clockless Computing. PowerPoint Presentation actually meant for a College Teaching in Engineering class. Meant for people without a lot of background in electrical engineering.

Automatic Layout Generation from a Cadence Digital Schematic. Tutorial on Automatic Place and Route software. Part of a larger body of design flow work I'm doing to integrate automatic digital design and synthesis techniques into the mixed signal group's design flows.

Synthesis with BuildGates Extreme. Tutorial on producing a Verilog netlist from a VHDL/Verilog behavioral or RTL model.

Silicon Ensemble Place & Route Tutorial. Tutorial for taking a Verilog netlist and generating a silicon layout.



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